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features eroflex circuit technology - advanced multichip modules ? scd3853 rev b 5/18/99 circuit technology www.aeroflex.com n 2 ? 128k x 8 srams & 2 ? 512k x 8 flash die in one mcm n access times of 25ns (sram) and 60ns (flash) or 35ns (sram) and 70 or 90ns (flash) n organized as 128k x 16 of sram and 512k x 16 of flash memory with separate data buses n both blocks of memory are user configurable as 512kx8 and 1mx8 respectively n low power cmos n input and output ttl compatible design n mil-prf-38534 compliant mcms available n decoupling capacitors and multiple grounds for low noise n industrial and military temperature ranges n industry standard pinouts n packaging ? hermetic ceramic l 66 pin, 1.08" x 1.08" x .160" pga type, no shoulder, aeroflex code# "p3" l 66 pin, 1.08" x 1.08" x .185" pga type, with shoulder, aeroflex code# "p7" l 68 lead, .94" x .94" x .140" single-cavity small outline gull wing, aeroflex code# "f18" (drops into the 68 lead jedec .99"sq cqfj footprint) n desc smd ? tbd flash memory features n sector architecture (each die) l 8 equal sectors of 64k bytes each l any combination of sectors can be erased with one command sequence n +5v programing, +5v supply n embedded erase and program algorithms n hardware and software write protection n internal program control time. n 10,000 erase / program cycles pin description fi/o 0-15 flash data i/o si/o 0-15 sram data i/o a 0?18 address inputs fwe 1-2 flash write enables swe 1-2 sram write enables fce 1-2 flash chip enables sce 1-2 sram chip enables oe output enable nc not connected v c c power supply gnd ground 128kx8 fce 2 oe a 0 ? a 18 si/o 0-7 si/o 8-15 fi/o 0-7 fi/o 8-15 8 8 8 8 fce 1 fwe 2 fwe 1 swe 2 swe 1 sce 1 sce 2 block diagram ? pga type packages (p3 & p7) & cqfp (f18) sram 128kx8 sram 512kx8 flash 512kx8 flash act?sf2816 high speed note: programming information available upon request 128kx16 sram / 512kx16 flash multichip module
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 2 absolute maximum ratings symbol rating range units t c operating temperature -55 to +125 c t stg storage temperature -65 to +150 c v g maximum signal voltage to ground -0.5 to +7 v t l maximum lead temperature (10 seconds) 300 c parameter flash data retention 10 years flash endurance (write/erase cycles) 10,000 normal operating conditions symbol parameter minimum maximum units v cc power supply voltage +4.5 +5.5 v v ih input high voltage +2.2 v cc + 0.3 v v il input low voltage -0.5 +0.8 v capacitance (v in = 0v, f = 1mhz, t c = 25c ) symbol parameter maximum units c a d a 0 ? a 18 capacitance 50 pf c o e oe capacitance 50 pf c w e 1,2 f/s write enable capacitance 20 pf c c e 1,2 f/s chip enable capacitance 20 pf c i / o i/o 0 ? i/o 15 capacitance 20 pf these parameters are guaranteed by design but not tested dc characteristics (v c c = 5.0v, v s s = 0v, tc = -55c to +125c, unless otherwise indicated) parameter sym conditions min max units input leakage current i li v cc = max, v in =0tov cc 10 a output leakage current i lo fce = sce = v ih , oe = v ih, v out =0tov cc 10 a sram operating supply current x 16 mode i cc x16 sce = v il , oe = v ih , f = 5mhz, v cc = max, fce = v ih 325 ma standby current i sb fce = sce = v ih , oe = v ih , f = 5mhz, v cc = max 40 ma sram output low voltage v ol i ol = 8 ma, v cc = min, fce = v ih 0.4 v sram output high voltage v oh i oh = -4.0 ma, , v cc = min, fce = v ih 2.4 v flash vcc active current for read (1) i cc1 fce = v il , oe = v ih , sce = v ih 130 ma flash vcc active current for program or erase (2) i cc2 fce = v il , oe = v ih , sce = v ih 150 ma flash output low voltage v ol i ol = 8 ma, v cc = min, sce = v ih 0.45 v flash output high voltage v oh i oh = -2.5 ma, , v cc = min, s ce = v ih 0.85 x v c c v flash low vcc lock out voltage v lko 3.2 v notes: 1) the i c c current listed includes both the dc operating current and the frequency dependent component (at 5mhz). the frequency component typically is less than 2ma/mhz, with oe at v i h 2) i c c active while embedded algorithim (program or erase) is in progress 3) dc test conditions: v i l = 0.3v, v i h = v c c - 0.3v
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 3 sram ac characteristics (v c c = 5.0v, v s s = 0v, tc= -55c to +125c) read cycle parameter symbol ?025 min max ?035 min max units read cycle time t rc 25 35 ns address access time t aa 25 35 ns chip select access time t ace 25 35 ns output hold from address change t oh 0 0 ns output enable to output valid t oe 15 20 ns chip select to output in low z * t clz 3 3 ns output enable to output in low z * t olz 0 0 ns chip deselect to output in high z * t chz 12 20 ns output disable to output in high z * t ohz 12 20 ns * parameters guaranteed by design but not tested write cycle parameter symbol ?025 min max ?035 min max units write cycle time t wc 25 35 ns chip select to end of write t cw 20 25 ns address valid to end of write t aw 20 25 ns data valid to end of write t dw 15 20 ns write pulse width t wp 20 25 ns address setup time t as 0 0 ns output active from end of write * t ow 0 0 ns write to output in high z * t whz 10 20 ns data hold from write time t dh 0 0 ns address hold time t ah 0 0 ns * parameters guaranteed by design but not tested truth table mode sce oe swe data i/o power standby h x x high z standby read l l h data out active output disable l h h high z active write l x l data in active
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 4 timing diagrams ? sram d i/o t rc t oh t aa data valid previous data valid t o e high z t o h z read cycle timing diagrams data valid t c l z sce oe t a c e t c h z undefined don?t care read cycle 2 ( swe = v i h ) write cycle ( sce controlled, oe = v i h ) t c w t a s t w p t d w t o w sce swe data valid write cycle ( swe controlled, oe = v i h ) d i/o ac test circuit i o l parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output timing reference level 1.5 v notes: 1) v z is programmable from -2v to +7v. 2) i o l and i o h programmable from 0 to 16 ma. 3) tester impedance z o =75 w. 4) v z is typically the midpoint of v o h and v o l . 5) i o l and i o h are adjusted to simulate a typical resistance load circuit. 6) ate tester includes jig capacitance. i o h to device under test v z ~ 1.5 v (bipolar supply) current source current source c l = 50 pf t w c t a w t a h t rc t a a t o l z s e e n o t e s e e n o t e s e e n o t e s e e n o t e note: guaranteed by design, but not tested. d i/o t d h t w h z s e e n o t e read cycle 1 ( sce = oe = v i l , swe = v i h ) write cycle timing diagrams t w p t d w data valid t w c t a w t a h d i/o t d h sce swe t c w t a s a 0-18 a 0-18 a 0-18 a 0-18 ac test conditions
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 5 flash ac characteristics ? read only operations (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max units read cycle time t a v a v t r c 60 70 90 ns address access time t a v q v t a c c 60 70 90 ns chip enable access time t e l q v t c e 60 70 90 ns output enable to output valid t g l q v t o e 30 35 35 ns chip enable to output high z (1) t e h q z t d f 20 20 20 ns output enable high to output high z(1) t g h q z t d f 20 20 20 ns output hold from address, ce or oe change, whichever is first t a x q x t o h 0 0 0 ns note 1. guaranteed by design, but not tested flash ac characteristics ? write / erase / program operations, f we controlled (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max units write cycle time t a v a c t w c 60 70 90 ns chip enable setup time t e l w l t c e 0 0 0 ns write enable pulse width t w l w h t w p 40 45 45 ns address setup time t a v w l t a s 0 0 0 ns data setup time t d v w h t d s 40 45 45 ns data hold time t w h d x t d h 0 0 0 ns address hold time t w l a x t a h 45 45 45 ns write enable pulse width high t w h w l t w p h 20 20 20 ns duration of byte programming operation t w h w h 1 14 typ 14 typ 14 typ s sector erase time t w h w h 2 30 30 30 sec read recovery time before write t g h w l 0 0 0 s vcc setup time t v c e 50 50 50 s chip programming time 50 50 50 sec chip enable hold time t o e h 1 10 10 10 ns chip erase time t w h w h 3 120 120 120 sec 1. toggle and data polling only. flash ac characteristics ? write / erase / program operations, fce controlled (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max units write cycle time t a v a c t w c 60 70 90 ns write enable setup time t w l e l t w s 0 0 0 ns chip enable pulse width t e l e h t c p 40 45 45 ns address setup time t a v e l t a s 0 0 0 ns data setup time t d v e h t d s 40 45 45 ns data hold time t e h d x t d h 0 0 0 ns address hold time t e l a x t a h 45 45 45 ns chip enable pulse width high t e h e l t c p h 20 20 20 ns duration of byte programming t w h w h 1 14 typ 14 typ 14 typ s sector erase time t w h w h 2 30 30 30 sec read recovery time t g h e l 0 0 0 ns chip programming time 50 50 50 sec chip erase time t w h w h 3 120 120 120 sec
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 6 ac waveforms for flash memory read operations t o h t c e t o e t a c c t r c t d f output valid high z high z outputs oe fwe fce addresses addresses stable fwe oe fce data addresses 5.0v 5555h pa data polling pa d7 d o u t pd aoh t w h w h 1 t o e t r c t c e t d f t o h t a h t a s t d h t w p h t w p t d s t c e t w c write/erase/program operation for flash memory, f we controlled notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the 0utput of the complement of the data written to the deviced. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t g h w l
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 7 ac waveforms chip/sector erase operations for flash memory data addresses v c c 5555h data polling t a h fce t a s fwe 5555h 5555h sa 2aaah 2aaah t g h w l t w p t w p h t d s t d h t c e t v c e 55h aah 80h 55h 10h/30h aah oe notes: 1. sa is the sector address for sector erase. ac waveforms for data polling during embedded algorithm operations for flash memory t o e t c h t w h w h 1 or 2 t o e t o h t d f t c e t o e h * * dq7=valid data (the device has completed the embedded operation). dq0?dq6=invalid dq 7 dq 7= valid data dq0?dq6 valid data high z fce dq7 oe fwe dq0-dq6
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 8 fwe oe fce data addresses 5.0v 5555h pa data polling pa d7 d o u t pd aoh t w h w h 1 t a h t a s t d h t c p h t c p t d s t w s t w c t g h w l notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the 0utput of the complement of the data written to the device. 4. d o u t is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. write/erase/program operation for flash memory, f ce controlled
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 9 pin numbers & functions 66 pins ? pga-type pin # function pin # function pin # function pin # function 1 si/o 8 18 a 12 35 fi/o 9 52 fwe 1 2 si/o 9 19 vcc 36 fi/o 10 53 fce 1 3 si/o 10 20 sce 1 37 a 6 54 gnd 4 a 13 21 nc 38 a 7 55 fi/o 3 5 a 14 22 si/o 3 39 nc 56 fi/o 15 6 a 15 23 si/o 15 40 a 8 57 fi/o 14 7 a 16 24 si/o 14 41 a 9 58 fi/o 13 8 a 17 25 si/o 13 42 fi/o 0 59 fi/o 12 9 si/o 0 26 si/o 12 43 fi/o 1 60 a 0 10 si/o 1 27 oe 44 fi/o 2 61 a 1 11 si/o 2 28 a 18 45 v c c 62 a 2 12 swe 2 29 swe 1 46 fce 2 63 fi/o 7 13 sce 2 30 si/o 7 47 fwe 2 64 fi/o 6 14 gnd 31 si/o 6 48 fi/o 11 65 fi/o 5 15 si/o 11 32 si/o 5 49 a 3 66 fi/o 4 16 a 10 33 si/o 4 50 a 4 17 a 11 34 fi/o 8 51 a 5 all dimensions in inches 1.085 sq 1.000 .600 typ 1.000 .100 typ .020 .016 .100 typ .165 min .160 pin 56 pin 66 pin 11 pin 1 bottom view (p7 & p3) max max .020 .016 .100 .025 .185 max side view (p7) side view (p3) .050 dia .035 typ typ typ typ "p7" ? 1.08" sq pga type package (with shoulders on pins 1, 11, 56 & 66) "p3" ? 1.08" sq pga type package standard (without shoulders ) .145 min
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 10 pin numbers & functions 68 pins ? dual-cavity cqfp pin # function pin # function pin # function pin # function 1 gnd 18 gnd 35 oe 52 gnd 2 fce 1 19 si/o 8 36 sce 2 53 fi/o 7 3 a 5 20 si/o 9 37 a 17 54 fi/o 6 4 a 4 21 si/o 10 38 swe 2 55 fi/o 5 5 a 3 22 si/o 11 39 fwe 1 56 fi/o 4 6 a 2 23 si/o 12 40 fwe 2 57 fi/o 3 7 a 1 24 si/o 13 41 a 18 58 fi/o 2 8 a 0 25 si/o 14 42 nc 59 fi/o 1 9 nc 26 si/o 15 43 nc 60 fi/o 0 10 si/o 0 27 v cc 44 fi/o 15 61 v c c 11 si/o 1 28 a 11 45 fi/o 14 62 a 10 12 si/o 2 29 a 12 46 fi/o 13 63 a 9 13 si/o 3 30 a 13 47 fi/o 12 64 a 8 14 si/o 4 31 a 14 48 fi/o 11 65 a 7 15 si/o 5 32 a 15 49 fi/o 10 66 a 6 16 si/o 6 33 a 16 50 fi/o 9 67 swe1 17 si/o 7 34 sce 1 51 fi/o 8 68 fce 2 .015 .002 .050 typ all dimensions in inches "f18" ? cqfp package .015 .990 sq .010 .950 sq max .800 ref see detail ?a? .002 pin 60 pin 44 pin 43 pin 27 pin 26 pin 10 pin 9 .890 sq max pin 61 .140 ref .640 sq ref .008 .002 detail ?a? .010 .008 .050 metal spacer ref
aeroflex circuit technology scd3853 rev b 5/18/99 plainview ny (516) 694-6700 11 ordering information model number desc smd number speed package act?sf2816n?26p3q tbd 25(s) / 60(f) ns 1.08"sq pga-type act?sf2816n?37p3q tbd 35(s) / 70(f) ns 1.08"sq pga-type act?sf2816n?39p3q tbd 35(s) / 90(f) ns 1.08"sq pga-type act?sf2816n?26p7q tbd 25(s) / 60(f) ns 1.08"sq pga-type act?sf2816n?37p7q tbd 35(s) / 70(f) ns 1.08"sq pga-type act?sf2816n?39p7q tbd 35(s) / 90(f) ns 1.08"sq pga-type act?sf2816n?26f18q tbd 25(s) / 60(f) ns .94"sq cqfp act?sf2816n?37f18q tbd 35(s) / 70(f) ns .94"sq cqfp act?sf2816n?39f18q tbd 35(s) / 90(f) ns .94"sq cqfp note: (s) = speed for sram, (f) = speed for flash part number breakdown act? s f 28 16 n? 26 p7 q aeroflex circuit technology memory type sf = sram flash combo module memory depth memory width, bits memory speed code package type & size c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screening * q = mil-prf-38534 compliant / smd screening * screened to the individual test methods of mil-std-883 surface mount packages thru-hole packages f18 = .94"sq 68 lead dual-cavity cqfp p3 = 1.085"sq pga 66 pins with out shoulder p7 = 1.085"sq pga 66 pins with shoulder 26 = 25ns sram & 60ns flash 37 = 35ns sram & 70ns flash 39 = 35ns sram & 90ns flash options, n = none 2 = 2m sram, 8 = locations aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: 1-(800) 843-1553 circuit technology specifications subject to change without notice.

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